1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a method for fabricating a capacitor of a semiconductor device.
2. Description of the Related Art
As the integration degree of semiconductor devices increases rapidly, technical difficulty increases as well. For example, a Dynamic Random Access Memory (DRAM) device necessarily requires a process for forming storage nodes having a high aspect ratio in order to provide a capacitor of a required capacitance due to design shrinkage. The storage node process is a process of forming hole-type openings by etching a mold layer and then forming storage nodes in the openings.
FIGS. 1A to 1D are cross-sectional views illustrating a conventional method for fabricating a capacitor of a semiconductor device.
Referring to FIG. 1A, an inter-layer dielectric layer 12 is formed over a substrate 11 where a predetermined structure is already formed. Subsequently, storage node contact plugs 13 penetrating through the inter-layer dielectric layer 12 are formed.
Subsequently, an etch stop layer 14, a mold layer 15, a support layer 16, a capping layer 17, and a hard mask pattern 18 are sequentially formed over the inter-layer dielectric layer 12. The etch stop layer 14 is formed of a material having an etch selectivity different from the mold layer 15, and the support layer 16 is formed of a material having an etch selectivity different from the mold layer 15 and the capping layer 17. The capping layer 17 prevents the support layer 16 from being lost during a process.
Subsequently, openings 19 that open the storage node contact plugs 13 are formed by using the hard mask pattern 18 as an etch mask and sequentially etching the capping layer 17, the support layer 16, the mold layer 15, and the etch stop layer 14. The hard mask pattern 18 may be removed by being lost during the process of forming the openings 19, or the hard mask pattern 18 may be removed through a process removing the hard mask pattern 18 after the openings 19 are formed.
Referring to FIG. 1B, after storage nodes 20 are formed in the openings 19, a sacrificial layer 21 for gap-filling the openings 19 is formed over the storage nodes 20.
Referring to FIG. 1C, a mask pattern (not shown) is formed over the substrate structure including the sacrificial layer 21, and then a support pattern 16A is formed by using the mask pattern (not shown) as an etch mask and etching the capping layer 17 and the support layer 16. The support pattern 16A prevents the storage nodes 20 from leaning during a subsequent dip-out process.
Referring to FIG. 1D, the capping layer 17, the sacrificial layer 21, and the mold layer 15 are removed. The mold layer 15 is removed through a dip-out process, and the support pattern 16A prevents the storage nodes 20 from leaning during the dip-out process. Subsequently, although not illustrated in the drawing, the formation of a capacitor may be completed by sequentially forming a dielectric layer and a plate electrode.
Recently, as the integration degree of semiconductor devices increases, the linewidth of the hole-type openings 19 continues to decrease when a process for forming storage node is performed. In order to form the openings 19 having a linewidth required by the semiconductor device, such methods as Extreme Ultraviolet ray (EUV) patterning technology, Spacer Patterning Technology (SPT), and Double Patterning Technology (DPT) are introduced. At this moment, the EUV patterning technology may take a few more years until EUV patterning equipment is brought to commercial use. Therefore, the EUV patterning technology may not be applied to the formation of the openings 19. For this reason, the openings are being formed through the spacer patterning technology or the double patterning technology.
However, it takes many procedural steps until the hard mask pattern 18 for defining the hole-type openings 19 are formed through the conventional spacer patterning technology or double patterning technology. Therefore, the productivity of using the conventional spacer patterning technology or double patterning technology is low, and there is a shortcoming that the openings 19 are hardly formed in a uniform linewidth. Also, when the openings 19 are formed through the spacer patterning technology or double patterning technology, the number of procedural steps taken to form the hard mask pattern 18 that defines the openings 19 increases by geometric progression as the linewidth of the openings 19 decreases. Thus, the above-mentioned problem becomes even worse.
In addition, because the support layer 16 and the capping layer 17 for protecting the support layer 16 are formed before the formation of the openings 19 according to the conventional technology, the burden for an etch process that is performed to form the openings 19 increases and it is difficult to control the sidewall profile of the openings 19.